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YMF752
AC'97 Rev2.1 Audio CODEC with SRC
OVERVIEW
Preliminary
YMF752 is an AC'97 Audio CODEC LSI, which is fully compliant with the industry standard "Audio CODEC '97" component specification (Revision 2.1). YMF752 includes a SRC (Sampling Rate Converter) for supporting variable sampling rate and an AC-Link serial interface. Therefore, YMF752 is the best audio solution for both laptops and desktop PCs as well as AMR (Audio Modem Riser) and MDC (Mobile Daughter Card). YMF752 also supports low power consumption while normal operating and allows for controlling the power down mode.
FEATURES
* AC'97 Revision 2.1 Compliant * Exceeds PC98 / PC99 Audio Performance Requirements * Analog Inputs: - 4 Stereo Inputs: LINE, CD, VIDEO, AUX - 2 Monaural Inputs: Speakerphone and PC BEEP Inputs - 2 Independent Microphone Inputs * PC BEEP can directly output to Line Out * Internal +20dB amplifier circuitry for microphone * Analog Outputs: Stereo LINE Output, True LINE Level and Monaural Output * Supports 3D Enhancement (Wide Stereo) * Supports Variable Sampling Rate (48k/44.1k/22.05k/16k/11.025k/8kHz) * Programmable Power Down Mode * Supports EAPD (External Amplifier Power Down) * Power Supplies: Analog 5.0V, Digital 3.3V * 48-Pin SQFP Package (YMF752-S) The following functions are supported by using the software driver from YAMAHA. * XG Wave Table Synthesizer * Downloadable Sound (DLS) * Legacy Audio (Sound Blaster Pro compatibility and FM Synthesizer) on Pure DOS
GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 compliant. XG logo is a trademark of YAMAHA Corporation. The contents of this catalog are target specifications and are subject to change without prior notice. When using this device, please recheck the specifications.
YAMAHA CORPORATION
YMF752 CATALOG 1998 Decembe 3, CATALOG No.:LSI-4MF752A02 July 2, 1999
YMF752
PIN CONFIGURATION
LNLVL_OUT_R
LNLVL_OUT_L
CODEC ID1#
CODEC ID0#
48
47
46
45
44
43
42
41
40
39
38
DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP
37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MONO_OUT
AVdd2
AVss2
EAPD
(N.C.)
(N.C.)
(N.C.)
TEST
LINE_OUT_R LINE_OUT_L TEST ENABLE CAP4 CAP3 CAP2 CAP1 Vrefout Vref AVss1 AVdd1
PHONE
VIDEO_R
CD_R
48-Pin SQFP Top View
2
LINE_IN_R
AUX_R
MIC1
VIDEO_L
CD_GND
CD_L
MIC2
LINE_IN_L
AUX_L
July 2, 1999
YMF752
PIN DESCRIPTION
No. Name I/O Digital power supply (+3.3V) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R AVdd1 AVss1 Vref Vrefout I O I I/O O I I AI AI AI AI AI AI AI AI AI AI AI AI AI AO AO Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to DVdd2. 24.576MHz Clock Input 24.576MHz Clock Output Digital ground. Connect this pin to DVss2. AC'97 Serial Input Stream AC'97 Bit Clock Digital ground. Connect this pin to DVss1. AC'97 Serial Output Stream Digital power supply (+3.3V) Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to DVdd1. SYNC Input (Fixed at 48kHz) Hardware Reset PC Speaker Beep Telephony Input AUX Input Left Channel AUX Input Right Channel Video Audio Input Left Channel Video Audio Input Right Channel CD Audio Input Left Channel CD Audio Analog Ground Connect this pin to CD Ground or Analog Ground. CD Audio Input Right Channel Microphone Input 1 Microphone Input 2 Line Input Left Channel Line Input Right Channel Analog Power Supply (+5.0V) Connect to the analog ground with 0.1mF and 47mF capacitors. Connect this pin to AVdd2. Analog ground. Connect this pin to AVss2. Analog Reference Voltage Connect to the analog ground with 0.1mF and 10mF capacitors. Analog Reference Voltage Output Function
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YMF752
No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name CAP1 CAP2 CAP3 CAP4 ENABLE TEST LINE_OUT_L LINE_OUT_R MONO_OUT AVdd2 LNLVL_OUT_L (N.C.) LNLVL_OUT_R AVss2 (N.C.) (N.C.) CODEC ID0# CODEC ID1# EAPD TEST I/O A A A A I+ I+ AO AO AO AO AO I+ I+ O O Capacitor Connection Pin Connect to the analog ground with a 560pF capacitor. Capacitor Connection Pin Connect to the analog ground with a 560pF capacitor. Capacitor Connection Pin Connect to the analog ground with a 1000pF capacitor. Capacitor Connection Pin Connect to the analog ground with 0.1mF and 10mF capacitors. Normally, do not connect externally. In case of "low" level, YMF752 do not operate. LSI Test Pin (Do not connect externally.) Line Output Left Channel Line Output Right Channel Monaural Output Analog power supply (+5.0V) Connect to the digital ground with 0.1mF and 47mF capacitors. Connect this pin to Avdd1. True LINE Level Output Left Channel Do not connect externally. True LINE Level Output Right Channel Analog ground. Connect to Avss1. Do not connect externally. Do not connect externally. CODEC ID (Do not connect externally.) CODEC ID (Do not connect externally.) External Amplifier Power Down LSI Test Pin (Do not connect externally.) Function
Note) AI: Analog Input Pin, AO: Analog Output Pin, I+: Input Pin with a Pull-up resistor
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YMF752
BLOCK DIAGRAM
DVdd(2)
VREF Power down Control
0dB/ +20dB
MUX
AVdd(2)
DVss(2)
AVss(2)
Vrefout
CAP4
CAP3
CAP2
CAP1
Vref
MIC1 MIC2 LINE_IN_R LINE_IN_L CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE
ENABLE EAPD RESET# SYNC BIT_CLK SDATA_OUT SDATA_IN CODEC ID0# CODEC ID1#
CD Right
BUF
A/D AC'97 SRC I/F
MUX
A/D
Record R 16step Record L 16step
MUX
CD Left
digital
D/A D/A
Volume Control
XTL_IN
XTL_OUT
PC Beep 16step PHONE 32step AUX 32step VIDEO 32step CD 32step LINE 32step MIC 32step
PC_BEEP
Timing Generator
Master L 32step Master R 32step LNLVL L 32step LNLVL R 32step
MUX
LINE_OUT_L LINE_OUT_R LNLVL_OUT_L LNLVL_OUT_R
MUX
Right
3D
5
MUX
PCM L 32step PCM R 32step
Left
Monaural 32step
MONO_OUT
July 2, 1999
YMF752
MIXER REGISTERS
NAME 00h 02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h Reset Master vol. LNLVL vol. Mute Mute 3D ML5-0 ML5-0 GL4-0 GL4-0 GL4-0 GL4-0 GL4-0 SL2-0 GL3-0 MIX D15 D14 D13 D12 D11 D10 D9 D8 D7 Reset MS LPBK 20dB
D6
D5
D4
D3
D2
D1
D0 Default
MR5-0 MR5-0 MM5-0 PV3-0 GN4-0 GN4-0 GR4-0 GR4-0 GR4-0 GR4-0 GR4-0 SR2-0 GR3-0 -
8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h N/A
Master vol. Mono Mute PC_BEEP vol. Phone vol. Mic vol. Line in vol. CD vol. Video vol. Aux vol. PCM out vol. Record Select Record Gain General Purpose 3D Control Power Down Mute Mute Mute Mute Mute Mute Mute Mute Mute POP EAPD
-
DP3-0 REF ANL DAC ADC -
PR6 PR5 PR4 PR3 PR2 PR1 PR0 ID0 AMAP
28h Extended Audio ID ID1 2Ah Ext'd audio Stat/Ctrl 2Ch 32h 7Ch 7Eh PCM DAC Rate PCM ADC Rate Vendor ID 1 -
-
VRA x201h VRA 0000h BB80h BB80h
-
SR15-0 SR15-0 Vendor ID
Vendor ID 2
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YMF752
SYSTEM CONNECTION DIAGRAM
Mono Out L-ch LNLVL Out R-ch LNLVL Out L-ch LINE Out R-ch LINE Out
PC Beep Phone L-ch AUX R-ch AUX L-ch Video R-ch Video L-ch CD CD Ground R-ch CD MIC L-ch Line IN R-ch Line IN
PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 LINE_IN_L LINE_IN_R MIC2
MONO_OUT LNLVL_OUT_L LNLVL_OUT_R LINE_OUT_L LINE_OUT_R
Vrefout
CAP1 CAP2 CAP3 CAP4 Vref
YMF752-S
AVdd1,2 AVss1,2 +5.0V
EAPD SDATA_IN SDATA_OUT BIT_CLK SYNC RESET# ID1# ID0# ENABLE XTL_IN XTL_OUT
DVdd1,2 DVss1,2
+3.3V
EAPD SDATA IN SDATA OUT BIT CLK SYNC RESET#
DGND AGND
1)
Power and Ground To get the most out of analog performance, it is necessary to split the ground into analog and digital blocks. Analog ground and digital ground earth at one point closed to the initial ground supply of the board. The layout of the ground pattern should be designed as large as possible and the impudence should be reduced to prevent from receiving ambient noise. In addition, use 0.1mF and 47mF capacitors to connect between the analog voltage pin and the analog ground as well as between the digital supply pin and the digital ground.
2)
Reference Voltage As the reference voltage determines all analog signals' reference levels of YMF752, noise generated from the reference voltage could affect the YMF752's analog performance. To stabilize the YMF752's reference voltage, insert a 0.1mF ceramic capacitor in parallel with a 10mF capacitor between Vref pin and the ground. The 0.1mF ceramic capacitor should be designed as close to the Vref pin as possible
3)
Master Clock To suppress the master clock from affecting its surroundings, it is recommended to keep the master clock guarded on the ground so the noise can be reduced.
4)
Unused Analog Input / Output pins For the unused analog input pins, short them through a 0.1mF ceramic capacitor to the analog ground. For the unused analog output pins, they should be left opened.
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YMF752
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Analog Supply Voltage Digital Supply Voltage Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Note) DVSS = AVSS = 0V Symbol AVDD DVDD VINA VIND TOP TSTG Min. -0.3 -0.3 -0.3 -0.3 0 -50 Max. 7.0 4.6 AVDD+0.3 DVDD+0.3 70 125 Unit V V V V C C
2. Recommended Operating Conditions
Parameter Analog Operating Voltage Digital Operating Voltage Operating Ambient Temperature Note) DVSS = AVSS = 0V Symbol AVDD DVDD TOP Min. 4.75 3.135 0 Typ. 5.00 3.30 25 Max. 5.25 3.465 70 Unit V V C
3. DC Characteristics
Parameter High Level 1 Input Voltage Low Level 1 Input Voltage High Level 2 Input Voltage Low Level 2 Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Pull-up Resistance Symbol VIH1 VIL1 VIH2 VIL2 VOH VOL ILI RUP Condition *1 *1 *2 *2 IOUT = 1mA Min. 0.7 DVDD 0.8 DVDD -10 50 Typ. 100 Max. 0.3 DVDD 0.2 DVDD 0.55 10 200 Unit V V V V V V A kW
IOUT = -1mA DVDD - 0.55
Note) TOP=0~70C, DVDD=3.30.165V, AVDD=5.00.25V, Capacitor load=50pF *1 : Apply to XTL_IN, RESET#, SYNC, SDATA_OUT and BIT_CLK *2 : Apply to CODEC ID0# and CODEC ID1#
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July 2, 1999
YMF752
4. AC Characteristics
4-1. Reset Parameter Cold Reset (SDATA_OUT="L", SYNC="L") RESET# active low pulse width RESET# inactive to BIT_CLK start up delay Warm Reset SYNC active high pulse width SYNC inactive to BIT_CLK start up delay Tsync_high Tsync2clk 1.0 162.8 1.3 s ns Trst_low Trst2clk 1.0 162.8 s ns Symbol Min. Typ. Max. Unit
Note) TOP=25C, AVDD=5.0V, Capacitor load=50pF Cold Reset
Trst2clk
Trst_low
RESET#
VIL
BIT_CLK
Warm Reset
Tsync2clk Tsync_high
SYNC
VIH
BIT_CLK
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July 2, 1999
YMF752
4-2. AC-link Interface Parameter BIT_CLK clock period BIT_CLK low pulse width BIT_CLK high pulse width BIT_CLK rise time BIT_CLK fall time SYNC period SYNC low pulse width SYNC high pulse width SYNC rise time SYNC fall time SDATA_IN, SDATA_OUT setup time SDATA_IN, SDATA_OUT hold time SDATA_IN delay time SDATA_IN rise time SDATA_IN fall time SDATA_OUT rise time SDATA_OUT fall time AC-link Low Power Mode End of slot 2 to BIT_CLK, SDATA_IN low Active Test Mode Setup to trailing edge of RESET# Rising edge of RESET# to Hi-Z Note) TOP=25C, AVDD=5.0V, Capacitor load=50pF BIT_CLK
Tclk_high Tclk_low
Symbol Tclk_period Tclk_low Tclk_high Trise_clk Tfall_clk Tsync_period Tsync_low Tsync_high Trise_sync Tfall_sync Tsetup Thold Tdelay Trise_din Tfall_din Trise_dout Tfall_dout Ts2_pdwn
Min. 36.0 36.0 10.0 10.0 -
Typ. 81.38 40.7 40.7 20.8 19.5 1.3 -
Max. 45.0 45.0 6 6 6 6 15.0 6 6 6 6 1.0
Unit ns ns ns ns ns s s s ns ns ns ns ns ns ns ns ns s
Tsetup2rst Toff
15.0 -
-
50
ns ns
BIT_CLK
Tclk_period
SYNC
Tsync_high Tsync_low
SYNC
Tsync_period
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July 2, 1999
YMF752
Setup and Hold
Tdelay Tsetup
BIT_CLK SDATA_IN
Thold
SDATA_OUT, SYNC
Signal Rise and Fall
Trise_clk Tfall_clk Trise_din Tfall_din
BIT_CLK
Trise_sync Tfall_sync
SDATA_IN
Trise_dout Tfall_dout
SYNC
SDATA_OUT
AC-link Low Power Mode
Slot1 Slot2
BIT_CLK SDATA_OUT
Write to 26h
Data PR4
Don't Care Ts2_pdown
SDATA_IN
Activate Test Mode
Tsetup2rst
RESET# SDATA_OUT
Toff
SDATA_IN, BIT_CLK
Hi-Z
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YMF752
5. Power Consumption
Parameter Normal Operating (26h : PR6-0 = "0") AVDD DVDD Power Down Mode (26h : PR6-0 = "1") AVDD DVDD Note) TOP=25C, DVDD=3.30.165V, AVDD=5.00.25V mA mA mA mA Min. Typ. Max. Unit
6. Analog Characteristics
Parameter Full Scale Line Input Full Scale Microphone Input (0dB) Full Scale Microphone Input (+20dB) Full Scale Line Output Analog S/N : CD to LINE_OUT Analog S/N : Others to LINE_OUT Analog Frequency Response S/N : D/A converter S/N : A/D converter THD : Line Output D/A & A/D Frequency Response Transition Band Stop Band Stop Band Rejection Out-of-Band Rejection Group Delay Power Supply Rejection Rate (1kHz) Crosstalk between Inputs Channels Attenuation & Gain Step PC_BEEP Other than PC_BEEP Input Impedance VREF Output Voltage 10 2.5 3.0 1.5 dB dB kW V 40 -70 20 19,200 28,800 85 40 1 20 85 75 96 86 0.02 19,200 28,800 90 Min. Typ. 1.0 1.0 0.1 1.0 102 102 20,000 Max. Unit Vrms Vrms Vrms Vrms dB dB Hz dB dB % Hz Hz Hz dB dB ms dB dB
Note) TOP=25C, DVDD=3.30.165V, AVDD=5.00.25V, 1kHz input sine wave
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YMF752
EXTERNAL DIMENSIONS
YMF752-S
9.000.40 7.000.30
36 25
37
24
7.000.30
48 13 1 12
0.200.10 or 0.180.10
P-0.5TYP
0 MIN. (STAND OFF)
1.40TYP or 1.45TYP
1.85MAX. (Installation height)
(1.0)
0-10
LEAD THICKNESS : 0.125TYP or 0.15TYP
0.500.20
The actual shape of the molded corner may slightly differ from the shape in this diagram. The figures in the parenthesis ( ) should be used as reference values. The dimensions of plastic body do not include burr of resin. Unit : mm (millimeters) Note : The LSIs for surface mounting need for special care on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha.
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9.000.40
July 2, 1999
YMF752
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE.
Note) The specifications of this product are subject to improvement change without prior notice.
AGENCY
YAMAHA CORPORATION
Address inquires to : Semi-conductor Sales Department
- Head Office 203, MatsunokiJima, Toyooka-mura. Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 YAMAHA System Technology. 100 Century Center Court, San Jose, CA 95112 Tel. +1-408-467-2300 Fax. +1-408-437-8791
- Tokyo Office - Osaka Office
- U.S.A. Office
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July 2, 1999

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